This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-239943, filed Aug. 26, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a nonvolatile ferroelectric memory, and more particularly to a nonvolatile ferroelectric memory having ferroelectric capacitors connected to the gates of field effect transistors having an MOS or MIS structure, and a method for manufacturing this memory.
In recent years, an MFS-FET (Metal Ferroelectric Semiconductor Field-Effect Transistor), in which the gate insulation film of a MOSFET is formed of a ferroelectric material, is expected as a key device for realizing a next-generation ferroelectric memory that does not require rewriting each time reading is executed. However, when an MFS capacitor or an MFS-FET is created by directly depositing a ferroelectric film on a substrate made of a semiconductor such as Si, counter diffusion occurs between components contained therein, thereby interrupting the formation of an electrically satisfactory interface.
To avoid this, generally used is an MFIS (Metal Ferroelectric materials Insulating materials Semiconductor) structure, in which an ordinary dielectric buffer layer is inserted between a ferroelectric film and a semiconductor substrate, or an MFMIS (Metal Ferroelectric material Metal Insulating material Semiconductor) structure, in which a conductive diffusion preventing layer is further inserted between the ferroelectric film and the buffer layer. In particular, in the latter structure, a ferroelectric capacitor is connected on a usual MOS- or MIS-FET, and is characterized in that the area ratio therebetween can be optimized.
Research on the optimization of the ratio between the area of the gate section of a MOS or MIS and the area of a ferroelectric capacitor is disclosed in, for example, a document xe2x80x9cMFMIS Structure for Nonvolatile Ferroelectric Memory Using PZT Thin Filmxe2x80x9d written by T. Kawasaki, Y. Akiyama, S. Fujita and S. Satoh, and published in IEICE TRANS. ELECTRON., VOL. E81-C, NO. 4, PP584-589 (APRIL 1998). Further, the inventors of the present invention have obtained experimental results as shown in FIG. 8.
FIGS. 8A and 8B illustrate examples of measurement results concerning the C-V (Capacitance-Voltage) characteristic, obtained by connecting, in series, a ferroelectric capacitor including SrBi2TaO9 and Pt electrodes, to a MOS capacitor. Hysteresis based on the ferroelectricity of the SrBi2TaO9 film is found in the C-V characteristic results shown in the figures. FIG. 8A shows a case where both capacitors have the same area, in which the width of hysteresis is narrow. On the other hand, FIG. 8B shows a case where the area of the MOS capacitor is four times that of the ferroelectric capacitor. In this case, the width of hysteresis is wide, which means a satisfactory characteristic.
As understood from the experimental results, the ferroelectric film usually used in a memory has a higher relative dielectric constant and can induce a larger amount of charge per unit area than, for example, an SiO2 layer that is typically used as a buffer layer. Accordingly, to effectively apply a voltage to the ferroelectric film and to balance the amount of charge, it is important to make the area of the MOS capacitor large and the area of the ferroelectric capacitor small. The same relationship is seen even if the MOS capacitor is replaced with a FET. In order to enhance the performance of an MFMIS-FET, it is necessary to increase the area of its gate section. The optimal area ratio between the gate section and the ferroelectric capacitor is generally about 3-10, although it depends upon a material or structure employed.
Three methods can be considered for increasing the area of the gate section of a MOS- or MIS-FETxe2x80x941. a method for increasing the channel length of the FET, 2. a method for increasing the channel width of the FET, and 3. a method for extending its gate electrode up to its source/drain region, with the channel length and channel width unchanged. However, the first method is disadvantageous in that the driving current of the FET decreases. The third method is disadvantageous in that its parasitic capacitance increases and hence its operation speed lowers. To increase the area of the gate section without raising such problems, it is important to increase the channel width, i.e. the gate width, as in the second method.
U.S. patent application Ser. No. 09/379,522 filed Aug. 23, 1999, by the same inventors as the present application, for example, discloses a nonvolatile ferroelectric memory of a structure in which MOS- or MIS-FETs are assembled by forming an Si thin film in stripes on an insulated substrate, and ferroelectric capacitors are provided on the resultant structure. In this memory structure, however, the gate width direction of each MOS- or MIS-FET is parallel to the Si stripes. Accordingly, if the gate width is widened, each FET occupies a long portion of each Si stripe, which makes it impossible to form a highly-integrated ferroelectric memory. Specifically, if the gate area is ten times the area of the ferroelectric capacitor, the degree of integration is reduced to about one tenth.
Thus, in the conventional nonvolatile ferroelectric memory, in order to enhance its performance, it is necessary to enlarge the gate area as compared to the ferroelectric capacitor area. However, the wider the gate width is made so as to increase the gate area, the lower the integration of the memory.
It is the object of the invention to provide a highly-integrated nonvolatile ferroelectric memory having an optimal element structure of high performance, which employs MOS- or MIS-FETs of a wide gate width.
The present invention provides a nonvolatile ferroelectric memory that comprises MOS-type or MIS-type field effect transistors assembled by a silicon thin film formed in stripes on an insulated substrate, and ferroelectric capacitors layered on the silicon thin film in the thickness direction thereof, wherein one or a plurality of ferroelectric capacitors are connected to the gate electrodes of the transistors, whereby the source, channel and drain regions of each transistor are formed in the thickness direction of the silicon thin film.
According to a first example of the invention, there is provided a nonvolatile ferroelectric memory, which employs a laminated structure wherein: an n-region, a p-region and another n-region (or a p-region, an n-region and another p-region) are formed in this order from the bottom in the thickness direction of the silicon thin film; an insulation film is provided on side walls of a hole formed in the silicon thin film and at least extending to the n-region (or p-region); the lower and upper n-regions (or p-regions) are used as the source and drain of the transistor, respectively; the intermediate p-region (or n-region) is used as the channel of the transistor; and the insulation film on the side walls of the hole is used as a gate insulation film.
According to a second example of the invention, there is provided a nonvolatile ferroelectric memory, in which: a silicon thin film has a laminated structure wherein an n-region and a p-region (or a p-region and an n-region) are formed in this order from the bottom in the thickness direction of the silicon thin film; a conductive electrode is provided on the silicon thin film in a direction substantially perpendicular to a direction in which the silicon thin film is formed in stripe; an insulation film is formed on the side walls of a hole formed in an intersection between the conductive electrode and the silicon thin film and extending from the upper surface of the conductive electrode at least to the lower n-region (or p-region); the lower n-region (or p-region) is used as the source or drain of a transistor; the p-region (or n-region) thereon is used as the channel of the transistor; the conductive electrode is used as the drain or source of the transistor; and the insulation film on the side walls of the hole is used as a gate insulation film.
According to a third example of the invention, there is provided a nonvolatile ferroelectric memory, in which a conductive electrode contains an impurity that serves as a donor or acceptor with respect to a silicon thin film; an n-region (or p-region) is formed on the conductive electrode by diffusing the impurity into the silicon thin film at an intersection portion by a heat treatment; and the n-region (or p-region) formed at the intersection portion by the heat treatment is used as the drain or source.
The conductive electrode is made of polysilicon, a metal silicide, or a pure metal, etc.
In the present invention, source, channel and drain regions are formed in a silicon thin film on an insulated substrate in the thickness direction of the thin film, thereby constituting a so-called tandem-type transistor. In this structure, the substantial gate width of each transistor can be widened without reducing the degree of integration. As a result, the nonvolatile ferroelectric memory including MOS- or MIS-type field effect transistors and ferroelectric capacitors connected thereto can have an optimal element structure of high performance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.